The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. In addition, many methods require the circuit to be powered. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type dies, transistors and other circuitry are located in a very thin epitaxially-grown silicon layer in a circuit side of the die. The circuit side of the die is arranged face-down on a package substrate. This orientation provides many operational advantages. However, due to the face-down orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the chip.
Since access to the transistors and circuitry in flip-chips is generally from the back side of the device, it is often necessary to mill through the back side and probe certain circuit elements in order to test the device. Milling through the back side is often difficult and time consuming. Moreover, circuitry and devices in integrated circuits including flip-chips and others, may potentially be damaged by milling processes. The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies.
The present invention is directed to a method and system for post-manufacturing analysis of a semiconductor device involving the imaging and detection of defects in the device using infrared (IR) thermography. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, substrate is removed from an integrated circuit die and a target region is exposed. A portion of the target region is heated with an infrared (IR) laser beam, and the target region is imaged using IR thermography. The image of the target region is compared to a reference image, and circuit damage is determined via the comparison.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.